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SPT7840
10-BIT, 10 MSPS, 100 mW A/D CONVERTER TECHNICAL DATA
JUNE 27, 2001
FEATURES
* * * * * * * * * * Monolithic 10 MSPS converter 100 mW power dissipation On-chip track-and-hold Single +5 V power supply TTL/CMOS outputs 5 pF input capacitance Low cost Tri-state output buffers High ESD protection: 3,500 V minimum Selectable +3 V or +5 V logic I/O
APPLICATIONS
* All high-speed applications where low power dissipation is required * Video imaging * Medical imaging * IR imaging * Scanners * Digital communications
GENERAL DESCRIPTION
The SPT7840 is a 10-bit monolithic, low-cost, ultralowpower analog-to-digital converter capable of minimum word rates of 10 MSPS. The on-chip track-and-hold function assures very good dynamic performance without the need for external components. The input drive requirements are minimized due to the SPT7840's low input capacitance of only 5 pF. Power dissipation is extremely low at only 100 mW typical (120 mW maximum) at 10 MSPS with a power supply of +5.0 V. The digital outputs are +3 V or +5 V, and are user selectable. The SPT7840 is pin-compatible with an entire
family of 10-bit, CMOS converters (SPT7835/40/50/55/60/ 61), which simplifies upgrades. The SPT7840 has incorporated proprietary circuit design* and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS-compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The SPT7840 is available in a 28-lead SOIC package over the industrial temperature range, and a 32-lead small (7 mm square) TQFP package over the commercial temperature range.
*Patent pending
BLOCK DIAGRAM
ADC Section 1 AIN 1:8 Mux T/H
AutoZero CMP
11-Bit SAR 11
11
D10 Overrange D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1
P1 P2 Timing P7 and Control Enable P8
DAC
CLK In
. . .
. . . ADC Section 7
ADC Section 2 ADC Section 8 T/H
AutoZero CMP
. . .
11-Bit SAR 11 DAC 11
. . . 11
11 11-Bit 8:1 Mux/ Error Correction
Data Valid
Ref In
Reference Ladder
D0 (LSB) VREF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages AVDD ...................................................................... +6 V DVDD ..................................................................... +6 V Input Voltages Analog Input .............................. -0.5 V to AVDD +0.5 V VREF .............................................................. 0 to AVDD CLK Input ............................................................... VDD AVDD - DVDD .................................................. 100 mV AGND - DGND .............................................. 100 mV Output Digital Outputs ................................................... 10 mA Temperature Operating Temperature ............................ -40 to 85 C Junction Temperature ........................................ 175 C Lead Temperature, (soldering 10 seconds) ....... 300 C Storage Temperature ............................ -65 to +150 C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, CLK=20 MHz, S=10MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
PARAMETERS Resolution DC Accuracy Integral Linearity Error (ILE) Differential Linearity Error (DLE) No Missing Codes Analog Input Input Voltage Range Input Resistance Input Capacitance Input Bandwidth Offset Gain Error Reference Input Resistance Bandwidth Voltage Range VRLS VRHS VRHS - VRLS (VRHF - VRHS) (VRLS - VRLF) Reference Settling Time VRHS VRLS Conversion Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits (ENOB) IN = 1 MHz IN = 5 MHz Signal-to-Noise Ratio (SNR) (without Harmonics) IN = 1 MHz IN = 5 MHz
TEST CONDITIONS
TEST LEVEL
MIN 10
SPT7840 TYP
MAX
UNITS Bits
VI VI VI VI IV V V V V VI V IV IV V V V V V VI IV IV V V 10 2 VRLS 50
1.0 0.5 Guaranteed VRHS 5.0 100 2.0 2.0 400 100 0 3.0 1.0 500 150 600 2.0 AVDD 5.0
LSB LSB
(Small Signal)
V k pF MHz LSB LSB MHz V V V mV mV Clock Cycles Clock Cycles MHz MHz Clock Cycles ns ps (p-p)
4.0 90 75 15 20
12 5 10
VI VI VI VI 53 52
9.1 9.0 58 57
Bits Bits dB dB
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ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, CLK=20 MHz, S=10 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
PARAMETERS Dynamic Performance Total Harmonic Distortion (THD) IN = 1 MHz IN = 5 MHz Signal-to-Noise and Distortion (SINAD) IN = 1 MHz IN = 5 MHz Spurious Free Dynamic Range Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage tRISE tFALL Output Enable to Data Output Delay Power Supply Requirements Voltages OVDD DVDD AVDD Currents AIDD DIDD Power Dissipation
TEST CONDITIONS
TEST LEVEL
MIN
SPT7840 TYP
MAX
UNITS
VI VI VI VI V VI VI VI VI V IOH = 0.5 mA IOL = 1.6 mA 15 pF load 15 pF load 20 pF load, TA = +25 C 50 pF load over temp. VI VI V V V V IV IV IV VI VI VI
59 56 52 51
63 59 57 56 63
dB dB dB dB dB V V A A pF V V ns ns ns ns V V V mA mA mW
2.0 -10 -10 5 3.5 0.4 10 10 10 22 3.0 4.75 4.75 5.0 5.25 5.25 12 12 120 0.8 +10 +10
IN = 1 MHz
5.0 5.0 9 11 100
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
LEVEL
I II III IV V VI
TEST PROCEDURE
100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
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SPECIFICATION DEFINITIONS
APERTURE DELAY Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. APERTURE JITTER The variations in aperture delay for successive samples. DIFFERENTIAL GAIN (DG) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential gain is the maximum variation in the sampled sine wave amplitudes at these DC levels. DIFFERENTIAL PHASE (DP) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential phase is the maximum variation in the sampled sine wave phases at these DC levels. EFFECTIVE NUMBER OF BITS (ENOB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits. SINAD - 1.76 N= 6.02 INPUT BANDWIDTH Small signal (50 mV) bandwidth (3 dB) of analog input stage. DIFFERENTIAL LINEARITY ERROR (DLE) Error in the width of each code from its theoretical value. (Theoretical = VFS/2N) INTEGRAL LINEARITY ERROR (ILE) Linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from -FS through +FS. The deviation is measured from the edge of each particular code to the true straight line. OUTPUT DELAY Time between the clock's triggering edge and output data valid. OVERVOLTAGE RECOVERY TIME The time required for the ADC to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. SIGNAL-TO-NOISE RATIO (SNR) The ratio of the fundamental sinusoid power to the total noise power. Harmonics are excluded. SIGNAL-TO-NOISE AND DISTORTION (SINAD) The ratio of the fundamental sinusoid power to the total noise and distortion power. TOTAL HARMONIC DISTORTION (THD) The ratio of the total power of the first 9 harmonics to the power of the measured sinusoidal signal. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal.
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Figure 1A - Timing Diagram 1
1
ANALOG IN CLOCK IN SAMPLING CLOCK (Internal)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
INVALID
VALID
DIGITAL OUT
1
2
3
4
5
6
7
8
9
10
11
DATA VALID
Figure 1B - Timing Diagram 2
tC tCH tCLK CLOCK IN tOD DATA OUTPUT Data 0 Data 1 Data 2 tCL
DATA VALID tS
tDAV
tDAV
Table I - Timing Parameters
DESCRIPTION Conversion Time Clock Period Clock High Duty Cycle Clock Low Duty Cycle Clock to Output Delay (15 pF Load) DAV Pulse Width Clock to DAV PARAMETERS tC tCLK tCH tCL tOD tDAV tS 16 MIN 2*tCLK 50 40 40 15 50 50 20 tCLK 21 26 60 60 25 TYP MAX UNITS ns ns % % ns ns ns
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TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
80
THD vs Input Frequency
80
Signal-to-Noise Ratio (dB)
Total Harmonic Distortion (dB)
70
70
S = 10 MSPS
60
S = 10 MSPS
60
50
50
40
40
30
30
20 100 101 102
20
Input Frequency (MHz)
100
Input Frequency (MHz)
101
102
SINAD vs Input Frequency
80
110
Total Power Dissipation vs Sample Rate Reference is excluded = 30 mW Typ
Signal-to-Noise and Distortion (dB)
70
S = 10 MSPS
60
90
Power Dissipation (mW)
100 101 102
70
50
40
50
30
30
20
Input Frequency (MHz)
10
0
5
10
Sample Rate (CLK/2) MHz
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Figure 2 - Typical Interface Circuit
Ref In (+4 V) VRHF VRHS VRLS VRLF VIN VIN VCAL CLK IN CLK DAV AVDD AGND D10 D9 D8 D7 D6 D5 OVDD OGND D4 D3 D2 D1 D0 EN DGND* DVDD
SPT7840
3.3/5
Interfacing Logics
3.3/5
+A5
Enable/Tri-State (Enable = Active Low) L1 DGND 3.3/5
+A5
AGND
+
10 F +5 V Analog +5 V Analog RTN
*To reduce the possibility of latch-up, avoid connecting the DGND pins of the ADC to the digital ground of the system.
10 F +5 V Digital RTN +5 V Digital
+
NOTES: 1) L1 is to be located as closely to the device as possible. 2) All capacitors are 0.1 F surface-mount unless otherwise specified. 3) L1 is a 10 H inductor or a ferrite bead.
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the stated device performance. Figure 2 shows the typical interface requirements when using the SPT7840 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING Fairchild suggests that both the digital and the analog supply voltages on the SPT7840 be derived from a single analog supply as shown in figure 2. A separate digital supply should be used for all interface circuitry. Fairchild suggests using this power supply configuration to prevent a possible latch-up condition on powerup.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in the block diagram. The design contains eight identical successive approximation ADC sections, all operating in parallel, a 16-phase clock generator, an 11-bit 8:1 digital output multiplexer, correction logic, and a voltage reference generator that provides common reference levels for each ADC section. The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as shown in table II.
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Table II - Clock Cycles
Clock 1 2 3 4 5-15 16 Operation Reference zero sampling Auto-zero comparison Auto-calibrate comparison Input sample 11-bit SAR conversion Data transfer
Figure 3 - Ladder Force/Sense Circuit
AGND +
VRHF VRHS
The 16-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by two clock cycles so that the analog input is sampled on every other cycle of the input clock by exactly one ADC section. After 16 clock periods, the timing cycle repeats. The sample rate for the configuration is one-half of the clock rate; e.g., for a 20 MHz clock rate, the input sample rate is 10 MHz. The latency from analog input sample to the corresponding digital output is 12 clock cycles. * Since only eight comparators are used, a huge power savings is realized. * The auto-zero operation is done using a closed loop system that uses multiple samples of the comparators' response to a reference zero. * The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section. * Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. * The total input capacitance is very low since sections of the converter that are not sampling the signal are isolated from the input by transmission gates. VOLTAGE REFERENCE The SPT7840 requires the use of a single external voltage reference for driving the high side of the reference ladder. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS. Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than 2 LSB can be obtained. In cases where wider variations in offset and gain can be tolerated, VREF can be tied directly to VRHF, and AGND can be tied directly to VRLF as shown in figure 4. Decouple
VRLS (0.075 V) VRLF (AGND) 0.0 V
VRLS + VRLF VIN All capacitors are 0.01 F
Figure 4 - Reference Ladder
+4.0 V External Reference VRHS (+3.91 V)
90 mV
R/2 R R
R R
R=30 W (typ) All capacitors are 0.01 F
R R
75 mV
R/2
force and sense lines to AGND with a .01 F capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account. The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS.
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Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF - VRHS = 2.25 % of (VRHF - VRLF) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS - VRLF = 1.9 % of (VRHF - VRLF) (typical). Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF, and VRLF is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V), and a 75 mV increase is seen at VRLS (= 0.075 V). ANALOG INPUT VIN is the analog input. The input voltage range is from VRLS to VRHS (typically 4.0 V) and will scale proportionally with respect to the voltage reference. (See voltage reference section.) The drive requirements for the analog inputs are very minimal when compared to most other converters due to the SPT7840's extremely low input capacitance of only 5 pF and very high input resistance of 50 k. The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. Figure 5 - Recommended Input Protection Circuit
+V AVDD
Upon powerup, the SPT7840 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10-bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon powerup of 500 sec for a 10 MHz sample rate. Once calibrated, the SPT7840 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7840 to remain in calibration. INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times. Figure 6 - On-Chip Protection Circuit
VDD
120 W
Analog
120 W
Pad
D1
Buffer
47 W D2
ADC
POWER SUPPLY SEQUENCING CONSIDERATIONS
V D1 = D2 = Hewlett-Packard HP5712 or equivalent
All logic inputs should be held low until power to the device has settled to the specific tolerances. Avoid power decoupling networks with large time constants that could delay VDD power to the device. CLOCK INPUT The SPT7840 is driven from a single-ended TTL-input clock. Because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. The device's sample rate is 1/2 of the input clock frequency. (See figure 1A timing diagram.)
CALIBRATION The SPT7840 uses an auto-calibration scheme to ensure 10-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 10-bit accuracy during device operation. This process is completely transparent to the user.
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DIGITAL OUTPUTS The digital outputs (D0-D10) are driven by a separate supply (OVDD) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7840's TTL/CMOScompatible outputs with the user's logic system supply. The format of the output data (D0-D9) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. These outputs can be switched into a tri-state mode by bringing EN high. Table III - Output Data Information
OVERRANGE OUTPUT CODE D10 D9-D0 +F.S. + 1/2 LSB 1 11 1111 1111 +F.S. -1/2 LSB 0 1 1 1 1 1 1 1 1 1O +1/2 F.S. 0 OO OOOO OOOO +1/2 LSB 0 00 0000 000O 0.0 V 0 00 0000 0000 (O indicates the flickering bit between logic 0 and 1.) ANALOG INPUT
OVERRANGE OUTPUT The OVERRANGE OUTPUT (D10) is an indication that the analog input signal has exceeded the positive fullscale input voltage by 1 LSB. When this condition occurs, D10 will switch to logic 1. All other data outputs (D0 to D9) will remain at logic 1 as long as D10 remains at logic 1. This feature makes it possible to include the SPT7840 in higher resolution systems.
EVALUATION BOARD
The EB7840 evaluation board is available to aid designers in demonstrating the full performance of the SPT7840. This board includes a reference circuit, clock driver circuit, output data latches, and an on-board reconstruction of the digital data. An application note describing the operation of this board, as well as information on the testing of the SPT7840, is also available. Contact the factory for price and availability.
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PACKAGE OUTLINES
28-Lead SOIC
INCHES MIN MAX 0.699 0.709 0.005 0.011 0.050 typ 0.018 typ 0.0077 0.0083 0.090 0.096 0.031 0.039 0.396 0.416 0.286 0.292 MILLIMETERS MIN MAX 17.75 18.01 0.13 0.28 1.27 typ 0.46 typ 0.20 0.21 2.29 2.44 0.79 0.99 10.06 10.57 7.26 7.42
28
IH
1
SYMBOL A B C D E F G H I
A F B C H D
G E
32-Lead TQFP
GH
A B
C
D
I J E F
SYMBOL A B C D E F G H I J K L
INCHES MIN MAX 0.346 0.362 0.272 0.280 0.346 0.362 0.272 0.280 0.031 typ 0.012 0.016 0.053 0.057 0.002 0.006 0.037 0.041 0.007 0 7 0.020 0.030
MILLIMETERS MIN MAX 8.80 9.20 6.90 7.10 8.80 9.20 6.90 7.10 0.80 BSC 0.30 0.40 1.35 1.45 0.05 0.15 0.95 1.05 0.17 0 7 0.50 0.75
K L
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PIN ASSIGNMENTS
AGND VRHF 1 2 28 D10 27 D9 26 D8 25 D7
PIN FUNCTIONS
Name AGND VRHF VRHS VRLS VRLF VCAL VIN AVDD DVDD DGND CLK EN D0-9 D10 DAV OVDD OGND
D10
Function Analog Ground Reference High Force Reference High Sense Reference Low Sense Reference Low Force Calibration Reference Analog Input Analog VDD Digital VDD Digital Ground Input Clock CLK = FS (TTL) Output Enable Tri-State Data Output, (D0=LSB) Tri-State Output Overrange Data Valid Output Digital Output Supply Digital Output Ground No Connect
VRHS 3 N/C 4
VRLS 5 VRLF VIN AGND VCAL 6 7 8 9
24 D6 23 D5
SOIC
22 21
OVDD OGND
20 D4 19 18 D3 D2
AVDD 10 DVDD 11 DGND 12 CLK 13 DAV 14
17 D1 16 15 D0 EN
AGND
AGND
VRHS 31
VRHF
VRLS 32
N/C
24 23 22 D7 D6 D5 OVDD OGND D4 D3 D2
D9
D8
29
25
30
26
27
28
VRLF VIN AGND AGND VCAL AVDD AVDD DVDD
1 2 3 4 5 6 7 8
TQFP
21 20 19 18 17
12
16
15 D0
10 DGND
14
13
11 DGND
ORDERING INFORMATION
PART NUMBER SPT7840SIS SPT7840SCT TEMPERATURE RANGE -40 to +85 C 0 to +70 C PACKAGE TYPE 28L SOIC 32L TQFP
9 DVDD
D1
EN
DAV
CLK
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
www.fairchildsemi.com
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
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